This invention relates generally to verification and equivalence checking for design blocks, such as design blocks for semiconductor devices, including microprocessors and related elements.
For designs of semiconductor devices, such as microprocessors, conventional methods of performing design simulation and verification are to model the design with a high level view, such as a RTL description and a separate low level view, such as a transistor schematic or net list. The high level view has the advantage of fast simulation and functional verification. However, simulation of the high level model does not guarantee correctness of a physical semiconductor device made in accordance with the corresponding transistor schematic. To provide improved quality testing, the transistor schematic view has been simulated. However, due to the very large number of transistor elements in commercial designs, full chip simulation is not economically practical. Even simulation of transistor schematic designs for a portion of the chip, full error detection coverage using conventional simulation is not available.
Another approach for verification of designs for certain classes of circuits, typically static combinational circuits, is known as formal equivalence checking. This approach uses mathematical models of stable outputs of networks of combinational logic. While this approach is useful for certain types of circuits, the technique is generally not applicable for circuits that have self-timing elements, such as memory arrays. Since memory arrays are often a significant portion of a design for a semiconductor device, it would be desirable to perform formal equivalence checking on memory arrays. The conventional methods do not address transient outputs within clock phases that are necessary for self timed circuits.
Accordingly, there is a need for an improved method and system to verify design blocks with multiple views.